June 16, 2026 — As the semiconductor industry pushes toward the limits of Moore’s Law, the spotlight has shifted from simple transistor scaling to the sophisticated realm of 3D system integration. At this week’s 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, a collaboration between imec—the world-renowned semiconductor research hub—and Sony Semiconductor Solutions Corporation (Sony) has introduced a transformative integration module designed to redefine backside interconnects.
The joint research team has unveiled a novel "local backside dielectric isolation" (local BDI) process. This breakthrough enables the creation of sub-100nm self-aligned through-silicon via (TSV) connections that promise to resolve the industry’s long-standing struggle with resistance, leakage, and alignment tolerance in 3D-stacked chips.
The Core Innovation: Solving the Backside Bottleneck
For years, the industry has relied on "via-middle" TSV processes to facilitate the complex communication required between the active frontside of a wafer and its backside. While functional, these traditional methods suffer from high aspect ratios, which introduce significant hurdles in metallization and electrical efficiency.
The local BDI module developed by imec and Sony replaces this conventional paradigm. By utilizing a self-aligned isolation structure formed locally at the intersection of the TSVs and the active frontside of the wafer, the new method dramatically improves the physical and electrical integrity of the connections.
According to technical specifications released at the symposium, the local BDI approach offers a 3x larger overlay window compared to traditional processes. This improvement effectively mitigates the risk of misalignment during the delicate manufacturing process, ensuring that high-density interconnects remain reliable even as chip architectures grow increasingly complex.
Chronology: From Concept to Validation
The development of the local BDI module is the result of intensive R&D efforts aimed at supporting the next generation of logic and memory devices. The evolution of this technology can be traced through several critical phases:
- Initial Research (Pre-2025): Recognizing the limitations of high-aspect-ratio TSVs in existing 3D stacking schemes, engineers at imec and Sony began exploring self-aligned isolation structures. The goal was to maintain high density while reducing electrical resistance.
- Module Development: The team successfully integrated the local BDI step into a standard CMOS process flow. This involved perfecting the conformal dielectric deposition and isotropic etching processes that occur after the standard Front-End-of-Line (FEOL), Middle-of-Line (MOL), and Back-End-of-Line (BEOL) stages.
- Experimental Validation: Using a standard cell configuration with a 115nm cell height, researchers tested the alignment tolerances and leakage currents. The results confirmed a 30nm tolerance for misalignment and superior isolation performance.
- Public Unveiling (June 2026): The technology was formally presented to the global semiconductor community at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, marking its readiness for potential industrial adoption.
Supporting Data and Technical Advantages
The implications of the local BDI module are best understood through the specific performance gains reported by the research team. When compared to conventional via-middle TSV processes, the improvements are substantial:
- Geometric Optimization: The local BDI process yields a 50% larger top and bottom critical dimension (CD). This simplification is vital, as it makes the TSV metallization process significantly more robust and less prone to manufacturing defects.
- Electrical Performance: By optimizing the dimensions, the team achieved a threefold improvement in electrical resistance. Lower resistance translates directly to lower power consumption and higher performance for high-speed processors and memory modules.
- Alignment Tolerance: In the highly competitive world of sub-100nm manufacturing, alignment is everything. The new process provides a 30nm tolerance for misalignment, a major leap forward that allows for higher manufacturing yields.
- Leakage Control: Despite the increase in TSV dimensions, the self-aligned structures maintain excellent isolation from the surrounding silicon substrate, keeping leakage currents within strict parameters.
- Versatility in Depth: Unlike other backside schemes that require the removal of bulk silicon, the local BDI method functions effectively with up to 500nm of remaining bulk silicon. This makes it particularly suitable for DRAM and other memory architectures where a thicker substrate is necessary.
Official Responses and Strategic Vision
The collaboration between imec and Sony underscores a strategic move toward modularizing semiconductor manufacturing to suit diverse application requirements.
Zsolt Tokei, Imec Fellow and Program Director of 3D System Integration, highlighted the significance of the transition from existing middle-of-line structures to the new TSV connections. "Starting from highly dense and narrow via connections already present in the wafer frontside, our module for the first time allows a transition to much wider TSV connections between the active frontside and the wafer backside," Tokei stated. "This simplifies the TSV metallization process and improves its resistance threefold."
He further emphasized the flexibility of the process: "As opposed to backside integration schemes that rely on removing the remaining bulk silicon, our module allows TSVs to connect through bulk Si with up to 500nm thickness. This is of interest for applications such as DRAM that make use of the relatively thick Si layer remaining at the wafer backside."
Takushi Shigetoshi, Senior Manager at Sony and lead author of the study, noted that the industry is at a crossroads regarding 3D integration. "3D integration is becoming increasingly important across a wide range of semiconductor applications," Shigetoshi remarked. "It is highly meaningful to develop a variety of backside connectivity schemes that can be selected according to the target application."
Implications for the Future of Semiconductors
The introduction of the local BDI module arrives at a critical juncture for the tech industry. As demand for artificial intelligence, advanced mobile processors, and high-capacity memory surges, the industry is increasingly reliant on 3D stacking to bypass the physical constraints of two-dimensional chip design.
Impact on Logic and Memory
The primary beneficiaries of this innovation will be high-performance logic devices (such as CPUs and GPUs) and memory architectures like HBM (High Bandwidth Memory). By providing a reliable, low-resistance path between the frontside and backside, the local BDI module enables designers to stack more memory closer to the logic, reducing latency and thermal bottlenecks.
A New Tool in the Semiconductor Toolbox
Imec’s role as a facilitator of innovation remains central here. By developing this module, they have provided a flexible "building block" that manufacturers can integrate into their existing production lines. This modular approach allows for rapid prototyping and deployment of 3D-stacked chips without requiring a total overhaul of the manufacturing ecosystem.
Sustainability and Efficiency
Beyond raw speed, the reduction in electrical resistance is a major win for energy efficiency. As data centers consume an increasing share of global electricity, any reduction in the power required for inter-chip communication is a significant contribution to the industry’s sustainability goals.
Conclusion: Setting the Standard for 2026 and Beyond
The joint research from imec and Sony marks a significant technical milestone. By solving the challenges of TSV metallization and alignment, the local BDI module provides a pathway to more reliable, efficient, and scalable 3D-stacked systems.
As the industry looks toward the next generation of silicon design, technologies that simplify the manufacturing process while enhancing electrical performance—like the local BDI module—will define the winners in the competitive semiconductor landscape. With its ability to handle thick silicon layers and its compatibility with standard CMOS flows, this breakthrough is poised to become a staple in the design of future high-performance computing components.
For more information on these developments, researchers and industry professionals are encouraged to review the full technical papers presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits.
