In the rapidly evolving landscape of hardware design, the barrier to entry for professional-grade Field Programmable Gate Array (FPGA) development has historically been defined by exorbitant costs. Engineering teams and hobbyists alike have long faced a "pay-to-play" reality where the silicon alone often costs more than the target budget for an entire project. However, a new initiative from Adiuvo Engineering, led by industry veteran Adam Taylor, is set to disrupt this status quo.
The company’s newly announced Explorer development board, priced at a startling $99, features the AMD Artix UltraScale+ AU7P FPGA. This price point is particularly aggressive, as it sits below the market cost of the individual FPGA chip when purchased in small quantities. By leveraging a unique partnership with AMD and pioneering advanced PCB design techniques, Adiuvo is making high-performance signal processing and embedded acceleration accessible to a wider demographic of engineers.
The Genesis of the Explorer Board: A Strategic Partnership
The existence of the Explorer board is the result of a symbiotic relationship between Adiuvo Engineering and AMD. AMD, seeking to expand the reach of its Artix UltraScale+ family, identified a critical need for a low-cost, high-capability development platform that could serve as a gateway for designers.
Adiuvo Engineering stepped in to provide the engineering heavy lifting. By assuming the responsibility for the board’s design, signal integrity, and manufacturing logistics, Adiuvo enabled AMD to push a powerful piece of silicon into the hands of developers who might otherwise be priced out of the UltraScale+ ecosystem. This collaboration represents a shift in strategy for chip manufacturers, who are increasingly recognizing that the long-term value of an FPGA architecture lies in the size and proficiency of the community surrounding it.
Chronology: From Concept to Production
The development of the Explorer board has been a meticulous, multi-year undertaking.
- Initial Prototyping (Mid-2026): Adiuvo Engineering manufactured the first ten prototype units in the United Kingdom to validate the feasibility of the design.
- The Beta Phase (October 2026): The company plans to release 100 beta boards to coincide with the "Horizons FPGA" conference in London. These units will serve as a pilot program for community feedback and early software development.
- Scaling Challenges: As with many hardware projects in the current climate, supply chain constraints and fluctuating FPGA lead times remain a looming variable. Adiuvo is monitoring these factors closely to ensure the transition to mass production remains on track.
- Mass Production (February 2027): The company is currently slated to begin a production run of 3,000 units, aiming to fulfill the initial demand for what is expected to be one of the most popular entry-level FPGA boards of the decade.
Supporting Data: Understanding the AU7P Architecture
To appreciate the value of the Explorer board, one must examine the capabilities of the AMD Artix UltraScale+ AU7P. While the marketing terminology regarding "System Logic Cells" can be nebulous, the hard technical specifications are undeniably robust:
- Logic Capacity: 37K Look-Up Tables (LUTs) and 75K flip-flops.
- Memory Resources: 108 Block RAM (BRAM) blocks, each offering 36kbits of capacity.
- Digital Signal Processing (DSP): 216 dedicated DSP48E2 slices, each featuring a 27×18-bit multiplier and a 48-bit accumulator.
- Connectivity: Four 12.5Gbps GTH serial transceivers.
This configuration is far from an "entry-level" toy. It is a highly capable engine for digital signal processing, machine vision, and real-time communications. Furthermore, because the AU7P is part of a scalable family, a design that begins on the Explorer board can be seamlessly migrated to larger members of the Artix UltraScale+ line—which scale up to 141K LUTs and 1200 DSP slices—without necessitating a complete architectural overhaul or a change in the underlying toolset.
The Software Ecosystem: RISC-V and MicroBlaze V
A critical component of any modern FPGA project is the soft-core processor. Recognizing the global shift toward open-source architectures, AMD has moved to implement its MicroBlaze V soft-core within the FPGA fabric.
MicroBlaze V is AMD’s implementation of the RISC-V 32-bit architecture. It supports the base instruction set alongside various extensions, including multiplication/division (M), atomic (A), floating-point (F), code-compression (C), and bit-manipulation (ZBa, ZBb, ZBc, and ZBs). For the developer, this means access to a massive, global library of RISC-V software and compilers.
The Explorer board comes bundled with a license for AMD’s Vivado Design Suite. Adiuvo Engineering is also committed to providing a comprehensive board support package (BSP), alongside power-management software and sample code. These resources are essential, as they lower the "time-to-first-blink" for engineers who are new to the Artix architecture.
Engineering Innovation: The "OTHV" Breakthrough
Perhaps the most impressive aspect of the Explorer board is the engineering prowess applied to its physical design. The Artix UltraScale+ AU7P is housed in an FCVA289 BGA package with a 0.5mm pin pitch. Standard industry practices would dictate the use of High Density Interconnect (HDI) technology—employing blind and buried vias—to route such a dense component. However, HDI manufacturing is prohibitively expensive for a $99 retail product.
Adam Taylor and his team utilized advanced signal-integrity and power-integrity simulations to implement Offset Through-Hole Vias (OTHVs). By placing these vias at the edge of the component pads, the team avoided the cost of HDI while maintaining the electrical performance required for the chip’s high-speed transceivers. This design choice is a masterclass in cost-optimized engineering, proving that expensive manufacturing processes can sometimes be bypassed through rigorous upfront simulation.
Implications for the FPGA Market
The launch of the Explorer board has significant implications for both professional and academic sectors:
- Democratization of DSP: With 216 DSP slices available at this price point, the Explorer board effectively threatens the market for standalone DSP chips. Engineers can now implement custom DSP algorithms in hardware, achieving performance levels that previously required much more expensive development kits.
- Hardware-Agnostic Skills: Adiuvo’s commitment to training—ranging from RTL creation to high-level synthesis—means the Explorer board is not just a tool, but an educational platform. By integrating AI-assisted coding (utilizing tools like ChatGPT and Claude) into their curriculum, Adiuvo is positioning the Explorer as the premier board for the next generation of AI-augmented hardware engineers.
- Future-Proofing: Because the board leverages standard interfaces—including four PMOD ports for sensors and two SYZYGY/Zmod ports for high-speed data acquisition—it is an ideal candidate for software-defined radio, industrial automation, and machine vision prototypes.
Official Perspective and Future Outlook
In a recent interview, Adam Taylor highlighted that while Adiuvo is primarily an engineering and training firm, the Explorer board represents their core philosophy: providing high-quality tools that empower engineers to bridge the gap between abstract concepts and real-world hardware.
The integration of a Raspberry Pi RP2040 microcontroller for power management is another noteworthy feature. While intended for system oversight, the inclusion of the RP2040 provides an additional layer of flexibility for users, assuming they navigate the board’s power architecture with caution.
As the industry looks toward the late 2027 production cycle, the Explorer board stands as a testament to the power of collaboration between silicon giants and agile design firms. For students, researchers, and professional engineers looking to sharpen their skills in FPGA design, this board is more than just a bargain—it is an invitation to master one of the most powerful and scalable architectures in the modern digital landscape. Whether one is experimenting with RISC-V soft cores or pushing the limits of signal processing, the Explorer board provides a robust, low-cost foundation that is likely to define the entry-level market for years to come.
